The present invention relates to a resin-sealed type semiconductor device having an LOC (Lead On Chip) structure and, more particularly, to a technique which is effective when applied to a thin, small-sized semi-conductor package having a TSOP (Thin Small Outline Package) structure or the like.
A typical resin-sealed type semiconductor device having an LOC structure comprises, as shown in FIG. 22 (see Japanese Patent Laid-Open No. 2-246125/1990), for example, a semiconductor chip 1 including a circuit and a plurality of external terminals formed over a major face of a semiconductor substrate; a plurality of leads, each including an inner lead portion 3A comprising inner leads 3A.sub.1 forming signal inner leads (a first region) and a common inner lead 3A.sub.2 for supplying a power voltage and a reference voltage (a second region: hereinafter referred to as the bus-bar leads or fixed potential leads), and an outer lead portion 3B formed integrally with the inner lead portions 3A; bonding wires 5 for electrically connecting the external terminals (pads) and the signal inner leads 3A.sub.1 and the bus-bar leads 3A.sub.2 of the inner lead portions 3A, respectively; and a sealer 2A for sealing the semiconductor chip 1, the inner lead portions 3A and the bonding wires 5. The signal inner leads 3A.sub.1 and the bus-bar leads 3A.sub.2 are arranged over the major face of the semiconductor chip 1, being separated therefrom by an insulating film 4, and the bus-bar leads 3A.sub.2 are arranged substantially in parallel with the major face of the semiconductor chip 1.